We are glad to announce ASICMiner's 4th generation chip. From the physical testing data
of our verification sample, BE300S, the silicon results matches the simulation results faithfully,
and even outperforms our simulation in some cases. BE300S achieved the lowest energy
consumption per gigahash in existing market, getting the joule/gh ratio down below 0.2.
Furthermore, our string-based power solution eliminates almost all power losses and almost
all electric components on the board. Therefore on-wall power consumption would be very close
to (on-chip power/PSU efficiency), and the overall system cost is squeezed to its minimum.
Name: BE300S (Sample)
Technology: TSMC 28nm HPC
Package: FCLGA 5mm x 5mm
On chip efficiency (first board): 3.0GH/s | 0.1872W/G
4.8GH/s | 0.2275W/G
5.2GH/s | 0.2469W/G
On board efficiency (average of 4 boards): 2.8GH/s | 0.1961W/G
3.2GH/s | 0.2026W/G
3.6GH/s | 0.2095W/G
4.0GH/s | 0.2145W/G
4.8GH/s | 0.2204W/G
5.2GH/s | 0.2257W/G
5.6GH/s | 0.2314W/G
6.4GH/s | 0.2363W/G
6.8GH/s | 0.2439W/G
7.2GH/s | 0.2495W/G
24 chip board efficiency: 118.56GH/s | 0.26W/G
155.04GH/s | 0.27W/G
176.64GH/s | 0.31W/G
273.60GH/s | 0.38W/G
With more accurate control on the variance between chips we could in principle gain less power consumption in advance.
We are still testing more voltage-frequency combinations, as well as more chips.
But the test results are stable and solid so far.
After the thorough testing of single chip boards, we are going to test boards with chained chips.
Single chip testing board picture:
Testing going on:
24 chips testing board picture:
More data and pictures are to be updated.
